Espressif Systems /ESP32-P4 /H264 /CONF

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Interpret as CONF

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CLK_EN)CLK_EN 0 (REC_RAM_CLK_EN2)REC_RAM_CLK_EN2 0 (REC_RAM_CLK_EN1)REC_RAM_CLK_EN1 0 (QUANT_RAM_CLK_EN2)QUANT_RAM_CLK_EN2 0 (QUANT_RAM_CLK_EN1)QUANT_RAM_CLK_EN1 0 (PRE_RAM_CLK_EN)PRE_RAM_CLK_EN 0 (MVD_RAM_CLK_EN)MVD_RAM_CLK_EN 0 (MC_RAM_CLK_EN)MC_RAM_CLK_EN 0 (REF_RAM_CLK_EN)REF_RAM_CLK_EN 0 (I4X4_REF_RAM_CLK_EN)I4X4_REF_RAM_CLK_EN 0 (IME_RAM_CLK_EN)IME_RAM_CLK_EN 0 (FME_RAM_CLK_EN)FME_RAM_CLK_EN 0 (FETCH_RAM_CLK_EN)FETCH_RAM_CLK_EN 0 (DB_RAM_CLK_EN)DB_RAM_CLK_EN 0 (CUR_MB_RAM_CLK_EN)CUR_MB_RAM_CLK_EN 0 (CAVLC_RAM_CLK_EN)CAVLC_RAM_CLK_EN 0 (IME_CLK_EN)IME_CLK_EN 0 (FME_CLK_EN)FME_CLK_EN 0 (MC_CLK_EN)MC_CLK_EN 0 (INTERPOLATOR_CLK_EN)INTERPOLATOR_CLK_EN 0 (DB_CLK_EN)DB_CLK_EN 0 (CLAVLC_CLK_EN)CLAVLC_CLK_EN 0 (INTRA_CLK_EN)INTRA_CLK_EN 0 (DECI_CLK_EN)DECI_CLK_EN 0 (BS_CLK_EN)BS_CLK_EN 0 (MV_MERGE_CLK_EN)MV_MERGE_CLK_EN

Description

General configuration register.

Fields

CLK_EN

Configures whether or not to open register clock gate.\0: Open the clock gate only when application writes registers\1: Force open the clock gate for register

REC_RAM_CLK_EN2

Configures whether or not to open the clock gate for rec ram2.\0: Open the clock gate only when application writes or reads rec ram2\1: Force open the clock gate for rec ram2

REC_RAM_CLK_EN1

Configures whether or not to open the clock gate for rec ram1.\0: Open the clock gate only when application writes or reads rec ram1\1: Force open the clock gate for rec ram1

QUANT_RAM_CLK_EN2

Configures whether or not to open the clock gate for quant ram2.\0: Open the clock gate only when application writes or reads quant ram2\1: Force open the clock gate for quant ram2

QUANT_RAM_CLK_EN1

Configures whether or not to open the clock gate for quant ram1.\0: Open the clock gate only when application writes or reads quant ram1\1: Force open the clock gate for quant ram1

PRE_RAM_CLK_EN

Configures whether or not to open the clock gate for pre ram.\0: Open the clock gate only when application writes or reads pre ram\1: Force open the clock gate for pre ram

MVD_RAM_CLK_EN

Configures whether or not to open the clock gate for mvd ram.\0: Open the clock gate only when application writes or reads mvd ram\1: Force open the clock gate for mvd ram

MC_RAM_CLK_EN

Configures whether or not to open the clock gate for mc ram.\0: Open the clock gate only when application writes or reads mc ram\1: Force open the clock gate for mc ram

REF_RAM_CLK_EN

Configures whether or not to open the clock gate for ref ram.\0: Open the clock gate only when application writes or reads ref ram\1: Force open the clock gate for ref ram

I4X4_REF_RAM_CLK_EN

Configures whether or not to open the clock gate for i4x4_mode ram.\0: Open the clock gate only when application writes or reads i4x4_mode ram\1: Force open the clock gate for i4x4_mode ram

IME_RAM_CLK_EN

Configures whether or not to open the clock gate for ime ram.\0: Open the clock gate only when application writes or reads ime ram\1: Force open the clock gate for ime ram

FME_RAM_CLK_EN

Configures whether or not to open the clock gate for fme ram.\0: Open the clock gate only when application writes or readsfme ram\1: Force open the clock gate for fme ram

FETCH_RAM_CLK_EN

Configures whether or not to open the clock gate for fetch ram.\0: Open the clock gate only when application writes or reads fetch ram\1: Force open the clock gate for fetch ram

DB_RAM_CLK_EN

Configures whether or not to open the clock gate for db ram.\0: Open the clock gate only when application writes or reads db ram\1: Force open the clock gate for db ram

CUR_MB_RAM_CLK_EN

Configures whether or not to open the clock gate for cur_mb ram.\0: Open the clock gate only when application writes or reads cur_mb ram\1: Force open the clock gate for cur_mb ram

CAVLC_RAM_CLK_EN

Configures whether or not to open the clock gate for cavlc ram.\0: Open the clock gate only when application writes or reads cavlc ram\1: Force open the clock gate for cavlc ram

IME_CLK_EN

Configures whether or not to open the clock gate for ime.\0: Open the clock gate only when ime work\1: Force open the clock gate for ime

FME_CLK_EN

Configures whether or not to open the clock gate for fme.\0: Open the clock gate only when fme work\1: Force open the clock gate for fme

MC_CLK_EN

Configures whether or not to open the clock gate for mc.\0: Open the clock gate only when mc work\1: Force open the clock gate for mc

INTERPOLATOR_CLK_EN

Configures whether or not to open the clock gate for interpolator.\0: Open the clock gate only when interpolator work\1: Force open the clock gate for interpolator

DB_CLK_EN

Configures whether or not to open the clock gate for deblocking filter.\0: Open the clock gate only when deblocking filter work\1: Force open the clock gate for deblocking filter

CLAVLC_CLK_EN

Configures whether or not to open the clock gate for cavlc.\0: Open the clock gate only when cavlc work\1: Force open the clock gate for cavlc

INTRA_CLK_EN

Configures whether or not to open the clock gate for intra.\0: Open the clock gate only when intra work\1: Force open the clock gate for intra

DECI_CLK_EN

Configures whether or not to open the clock gate for decimate.\0: Open the clock gate only when decimate work\1: Force open the clock gate for decimate

BS_CLK_EN

Configures whether or not to open the clock gate for bs buffer.\0: Open the clock gate only when bs buffer work\1: Force open the clock gate for bs buffer

MV_MERGE_CLK_EN

Configures whether or not to open the clock gate for mv merge.\0: Open the clock gate only when mv merge work\1: Force open the clock gate for mv merge

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